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ISL6253
Data Sheet August 2004 FN9117.2
Highly Integrated Battery Charger for Notebook Computers
The ISL6253 is a highly integrated battery charger controller for Li-Ion/Li-Polymer batteries. High Efficiency is achieved by a synchronous buck topology and the use of a MOSFET, instead of a diode, for selecting power from the adapter or battery. The low side MOSFET emulates a diode at light loads to improve the light load efficiency and prevent system bus boosting. The constant output voltage can be selected for 2, 3 or 4 series Li-Ion cells with 0.5% accuracy over temperature. It can also be programmed between 4.2V +5% per cell and 4.2V -5% per cell to optimize battery capacity. When supplying the load and battery charger simultaneously, the input current limit for the AC adapter is programmable to within 3% accuracy to avoid overloading the AC adapter, and to allow the system to make efficient use of available adapter power for charging. It also has programmable charging current with 4% accuracy. The ISL6253 provides outputs that are used to monitor the current drawn from the AC adapter, and to monitor for the presence of an AC adapter. The ISL6253 automatically transitions from regulating current to regulating voltage. A conditioning charge feature provides approximately 10% of full scale charge current to safely charge deeply discharged lithiumion (LI+) battery packs when the battery voltage is below 3.0V/cell. ISL6253 has a feature of automatic power source selection by switching to the battery when the AC adapter is removed or switching to the AC adapter when the AC adapter is available. It also supports aircraft power applications while powering the system and not charging the battery.
Features
* 0.5% Voltage Accuracy * 3% Input Current Limit Accuracy * 4% Accurate Battery Charge Current Limit * Programmable Charge Limit Current, Adaptor Current Limit and Charge Voltage * Fixed 300kHz PWM Synchronous Buck Controller with Diode Emulation at Light Load * Output for Current Drawn from the AC Adapter * AC Adapter Present Indicator * Fast Input Current Limit Response * Input Voltage Range 7V to 25V * Up to 17.6V Battery-Voltage Set Point * Trickle Charge Mode When Battery Voltage is below 3.0V/Cell * Supports 2, 3 and 4 Cell Battery Packs * Control Adapter Power Source Select MOSFET * Thermal Shutdown * Aircraft Power Capable * DC Adapter Present Indicator * Battery Discharge MOSFET Control * Less than 10A Battery Leakage Current * QFN Package - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile * Pb-free Available
Ordering Information
PART # ISL6253HRZ (Note 1) ISL6253HAZ (Note 1) NOTES: 1. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. 2. Add "-T" for Tape and Reel. TEMP. RANGE (C) -10 to 100 -10 to 100 PACKAGE 28 Ld 5x5 QFN (Pb-free) 28 Ld QSOP (Pb-free) PKG. DWG. # L28.5x5 M28.15
Applications
* Notebook, Desknote and Sub-notebook Computers * Personal Digital Assistants
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6253 Pinouts
ISL6253 (28 LD QFN) TOP VIEW
DCPRN ACPRN DCSET ACSET CSON DCIN VDD DCIN VDD ACSET 21 20 19 18 17 16 15 8 ACLIM 9 VADJ 10 GND 11 PGND 12 LGATE 13 VDDP 14 BOOT CSOP CSIN CSIP SGATE BGATE PHASE UGATE DCSET EN CELLS ICOMP VCOMP ICM ICM VREF CHLIM 5 6 7 VREF CHLIM ACLIM VADJ GND
ISL6253 (28 LD QSOP) TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 DCPRN 27 ACPRN 26 CSON 25 CSOP 24 CSIN 23 CSIP 22 SGATE 21 BGATE 20 PHASE 19 UGATE 18 BOOT 17 VDDP 16 LGATE 15 PGND
28 EN CELLS ICOMP VCOMP 1 2 3 4
27
26
25
24
23
22
2
ISL6253
Absolute Maximum Ratings
DCIN, CSIP, DCPRN, ACPRN, CSON to GND . . . . . . -0.3V to +28V CSIP-CSIN, CSOP-CSON . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V CSIP-SGATE, CSIP-BGATE . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V PHASE to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7V to 28V BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +35V BOOT-PHASE, VDD-GND, VDDP-PGND . . . . . . . . . . . . -0.3V to 7V ICM, ICOMP, VCOMP . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V ACSET and DCSET to GND (Note 3) . . . . . . . . -0.8V to VDD+0.3V VDDP, ACLIM, CHLIM, VREF, CELLS. . . . . . . . -0.3V to VDD+0.3V EN, VADJ, PGND to GND . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V UGATE. . . . . . . . . . . . . . . . . . . . . . . . . PHASE-0.3V to BOOT+0.3V LGATE . . . . . . . . . . . . . . . . . . . . . . . . . . PGND-0.3V to VDDP+0.3V
Thermal Information
Thermal Resistance
JA (C/W) JC (C/W)
QFN Package (Notes 4, 6). . . . . . . . . . 39 9.5 QSOP Package (Note 5) . . . . . . . . . . . 80 NA ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Junction Temperature Range. . . . . . . . . . . . . . . . . .-10C to +150C Operating Temperature Range . . . . . . . . . . . . . . . .-10C to +100C Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Lead Temperature (soldering, 10s).. . . . . . . . . . . . . . . . . . . . +300C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress ratings only and operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
NOTES: 3. When the voltage across ACSET and DCSET is below 0V, the current through ACSET and DCSET should be limited less than 1mA. 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, VREF = ACLIM = CHLIM, VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, CVDD = 1F IVDD = 0mA, TA = -10C to +100C, TJ 125C, unless otherwise noted. TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SUPPLY AND BIAS REGULATOR DCIN Input Voltage Range DCIN Quiescent Current DCIN Quiescent Current in Shutdown mode Battery Leakage Current (Note 5) VDD Output Voltage/Regulation VDD Undervoltage Lockout Trip Point
7 EN = VDD, 7V < DCIN < 25V EN = 0, 7V < DCIN < 25V DCIN = 0, no load 7V < DCIN < 25 V, 0 < IVDD < 30mA Rising Hysteresis O < IVREF < 300A CSON = 16.8V, CELLS = VDD, VADJ = Float CSON = 12.6V, CELLS = GND, VADJ = Float CSON = 8.4V, CELLS = FLOAT, VADJ = Float CSON = 17.64V, CELLS = VDD, VADJ = VREF 4.925 4.2 100 2.365 -0.5 -0.55 -0.55 -0.6 -0.6 -0.6 -0.6 -0.6 -0.6 1.6 1.3 2 5.075 4.4 250 2.390 0 0 0 0 0 0 0 0 0
25 4 3 10 5.225 4.6 400 2.415 0.5 0.55 0.55 0.6 0.6 0.6 0.6 0.6 0.6
V mA mA A V V mV V
Reference Output Voltage VREF
Battery Charge Voltage Accuracy
CSON = 13.23V, CELLS = GND, VADJ = VREF CSON = 8.82V, CELLS = FLOAT, VADJ = VREF CSON = 15.96V, CELLS = VDD, VADJ = GND CSON = 11.97V, CELLS = GND, VADJ = GND CSON = 7.98V, CELLS = FLOAT, VADJ = GND
%
TRIP POINTS ACSET Threshold ACSET Input Bias Current Hysteresis ACSET Input Bias Current ACSET Input Bias Current DCSET Threshold ACSET > 1.26V ACSET < 1.26V 1.235 2 2 -1 1.235 1.26 3.4 3.4 0 1.26 1.285 4.8 4.8 1 1.285 V A A A V
3
ISL6253
Electrical Specifications
DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, VREF = ACLIM = CHLIM, VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, CVDD = 1F IVDD = 0mA, TA = -10C to +100C, TJ 125C, unless otherwise noted. (Continued) TEST CONDITIONS DCSET 1.26V DCSET < 1.26V MIN 2 2 -1 TYP 3.4 3.4 0 MAX 4.8 4.8 1 UNITS A A A
PARAMETER DCSET Input Bias Current Hysteresis DCSET Input Bias Current DCSET Input Bias Current OSCILLATOR Frequency PWM Ramp Voltage (peak-peak) CSIP = 18V CSIP = 11V SYNCHRONOUS BUCK REGULATOR Maximum Duty Cycle UGATE Pull-up Resistance UGATE Source Current UGATE Pull-down Resistance UGATE Sink Current LGATE Pull-up Resistance LGATE Source Current LGATE Pull-down Resistance LGATE Sink Current CHARGING CURRENT SENSING AMPLIFIER Input Common Mode Range Input Offset Voltage Input Bias Current at CSOP Input Bias Current at CSON CSOP to CSON Input Full Scale Sense Voltage 300kHz
240 1.4 0.8
300 1.55 0.9
360 1.7 1.0
kHz V V
97
99 1.8 1.0 0.9 1.8 1.8 1.0 0.9 1.8
99.6 3.0
% A A A A
BOOT-PHASE = 5V, 500mA source current BOOT-PHASE = 5V, BOOT-UGATE = 2.5V BOOT-PHASE = 5V, 500mA sink current BOOT-PHASE = 5V, UGATE-PHASE = 2.5V VDDP-PGND = 5V, 500mA source current VDDP-PGND = 5V, VDDP-LGATE = 2.5V VDDP-PGND = 5V, 500mA sink current VDDP-PGND = 5V, LGATE = 2.5V
1.8
3.0
1.8
0 Guarantee by design 0 < CSOP < 18V 0 < CSON < 18V CHLIM = 3.3V CHLIM = VREF CHLIM = FLOAT CHLIM = GND 123 96 61 26 6 4.0 2.5 1.5 3.0 20 -25 -3 0 10 300 127 100 65 30 8.9 7.5 5.6 3.7 3.1 100
18 3 20 425 131 104 69 34 12.0 11.0 9.0 7.0 3.2 180 25
V mV A A mV mV mV mV mV mV mV mV V/CELL mV/CELL A
CSOP to CSON Input Full Scale Sense Voltage in Trickle CHLIM = 3.3V Charge Mode CHLIM = VREF CHLIM = FLOAT CHLIM = GND Trickle Charge Threshold Voltage CSON Rising Hysteresis CHLIM Input Bias Current ADAPTER CURRENT SENSING AMPLIFIER Input Common Mode Range Input Offset Voltage Input Bias Current at CSIP Input Bias Current at CSIN ADAPTER CURRENT LIMIT THRESHOLD CSIP to CSIN Input Full Scale Sense Voltage ACLIM = VREF ACLIM = Float ACLIM = GND Guarantee by design 0 < CSIP < DCIN 0 < CSIN < DCIN CHLIM = GND or VREF
7 -2 325 1
25 2 475 10
V mV A A
100 75 50
103 78 53
106 81 56
mV mV mV
4
ISL6253
Electrical Specifications
DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET = DCSET = 1.5V, VREF = ACLIM = CHLIM, VADJ = Floating, EN = VDD = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, CVDD = 1F IVDD = 0mA, TA = -10C to +100C, TJ 125C, unless otherwise noted. (Continued) TEST CONDITIONS ACLIM = GND, or VREF MIN -25 TYP MAX 25 UNITS A A/V V A/V A/V 4 V
PARAMETER ACLIM Input Bias Current VOLTAGE REGULATION ERROR AMPLIFIER Error Amplifier Trans-conductance from CSON to VCOMP VCOMP Voltage Range CURRENT REGULATION ERROR AMPLIFIER Charging Current Error Amplifier Trans conductance Adapter Current Error Amplifier Trans conductance ICOMP Voltage Range BATTERY CELL SELECTOR CELLS Input Low Voltage CELLS Input Float Voltage CELLS Input High Current MOSFET DRIVER BGATE Pull-up Current BGATE Pull-down Current CSIP-BGATE Voltage High CSIP-BGATE Voltage Low DCIN-CSON Threshold for CSIP-BGATE Going High DCIN-CSON Threshold for CSIP-BGATE Going Low DCIN-CSON Threshold Hysteresis SGATE Pull-up Current SGATE Pull-down Current CSIP-SGATE Voltage High CSIP-SGATE Voltage Low CSIP-CSIN Threshold for CSIP-SGATE Going High CSIP-CSIN Threshold Hysteresis LOGIC INTERFACE EN Low Level Input Voltage EN High Level Input Voltage ACPRN Sink Current ACPRN Leakage Current DCPRN Sink Current DCPRN Leakage Current ICM Output Voltage Thermal Shutdown Temperature Thermal Shutdown Temperature Hysteresis NOTE:
CELLS = VDD
20 0.3
30
40 4
50 50 0.3
0.5 CELLS = Float VREF -0.3 VDD0.5 VREF VREF + 0.3
V V V
CSIP-BGATE = 3V CSIP-BGATE = 5V
1 3.25 8.0
1.4 5.0 10 0
2 7 12 0.1 200 500 400 2.0 350 15 0.1 15 6
mA mA V V mV mV mV mA A V V mV mV
DCIN = 12V, CSON Rising DCIN = 12V, CSON Falling
-200 0 250
0 300 300 1.4 150 8.5 0
CSIP-SGATE = 3V CSIP-SGATE = 2.5V
1.0 40 5
3 1
8.5 2
0.8 2.0 ACPRN = 0.4V ACPRN = 20V DCPRN = 0.4V DCPRN = 20V Iload = 0 to 100A, CSIP-CSIN = 103mV Rising 3 -1 3 -1 1.885 1.980 150 20 8 8 13 1 13 1 2.085
V V mA A mA A V C C
7. This is sum of currents in these pins (CSIP, CSIN, BOOT, UGATE, PHASE, CSOP and CSON) tied together to 18V. EN, ACSET, DCSET, VADJ, CELLS, ACLIM, CHLIM, VDD, DCIN = 0.
5
ISL6253 Typical Operating Performance
Circuit of Figure 18, VDCIN = 20V, 4S2P Li-Ion Battery, TA = 25C, unless otherwise noted.
VDD LOAD REGULATION ACCURACY (%) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.03 -0.6 -0.7 -0.04 VDCIN = 20V VDD = 5.075V EN = 0 VDD ACCURACY (%) 0.01 VDD =5.075V IVDD = 0mA 0
-0.01
-0.02
0
5
10 15 20 LOAD CURRENT (mA)
25
30
5
10 15 20 INPUT VOLTAGE VDCIN (V)
25
FIGURE 1. VDD LOAD REGULATION
FIGURE 2. VDD LINE REGULATION
5.0
17.0
CHARGE CURRENT (A)
BATTERY VOLTAGE (V)
4.0
16.0
LOAD CURRENT 5A/DIV ADAPTER CURRENT 5A/DIV CHARGE CURRENT 2A/DIV
3.0
15.0
2.0
14.0
1.0
13.0
BATTERY VOLTAGE 2V/DIV t: 1ms/DIV, CHLIM = ACLIM = VREF LOAD STEP: 0A TO 4A CHARGE CURRENT = 3A AC ADAPTER CURRENT LIMIT = 5A
0.0 0 26 50 75 99 TIME (MINUTE)
12.0
FIGURE 3. BATTERY CHARGE V-I CHARACTERISTICS
FIGURE 4. LOAD TRANSIENT RESPONSE
INDUCTOR CURRENT 1A/DIV VDCIN 10V/DIV BATTERY VOLTAGE 10V/DIV CHARGE CURRENT 1A/DIV ICM ACCURACY (%)
5 EN=0 0
-5
-10
-15 t: 10ms/DIV CHARGE CURRENT: 2.6A INPUT VOLTAGE STEP: 18.0V TO 25V LOAD CURRENT: 1A
-20
0
1
2 3 AC ADAPTER CURRENT (A)
4
5
FIGURE 5. LINE TRANSIENT RESPONSE
FIGURE 6. ICM ACCURACY vs AC ADAPTER CURRENT
6
ISL6253 Typical Operating Performance (Continued) Circuit of Figure 18, VDCIN = 20V, 4S2P Li-Ion Battery, TA = 25C, unless otherwise noted.
EN 5V/DIV
INDUCTOR CURRENT 2A/DIV
SYSTEM BUS VOLTAGE 5V/DIV BGATE-CSIP 2V/DIV BGATE-CSIP 2V/div INDUCTOR CURRENT 2A/DIV t: 0.5ms/DIV t: 0.5ms/DIV
SGATE-CSIP SGATE-CSIP 2V/DIV 2V/div 2V/DIV
BATTERY VOLTAGE 2V/DIV
FIGURE 7. CHARGE ENABLE AND SHUTDOWN
FIGURE 8. AC ADAPTER INSERTION
BGATE-CSIP 2V/DIV
LOAD CURRENT = 2A INDUCTOR CURRENT 2A/DIV BATTERY VOLTAGE 10V/DIV
SYSTEM BUS VOLTAGE 5V/DIV SGATE-CSIP 2V/DIV
ICOMP INDUCTOR CURRENT 2A/DIV t: 5s/DIV VCOMP 2V/DIV
t: 1ms/DIV
FIGURE 9. AC ADAPTER REMOVAL
FIGURE 10. BATTERY INSERTION
VPHASE 10V/DIV
BATTERY VOLTAGE 2V/DIV
VCSON 10V/DIV
INDUCTOR CURRENT 1A/DIV
INDUCTOR CURRENT 2A/DIV CHARGE CURRENT 1A/DIV t: 20s/DIV t: 0.1ms/DIV
FIGURE 11. BATTERY REMOVAL
FIGURE 12. CHARGE MODE TRANSITION FROM TRICKLE MODE TO CONSTANT CURRENT MODE
7
ISL6253 Typical Operating Performance (Continued) Circuit of Figure 18, VDCIN = 20V, 4S2P Li-Ion Battery, TA = 25C, unless otherwise noted.
PHASE 10V/DIV VDCIN = 20V VDCIN=20V VCSON = 16.8V VCSON=16.8V PHASE 10V/DIV
UGATE UGATE UGATE LGATE 2V/DIV
LGATE LGATE
INDUCTOR CURRENT 0.5A/DIV
CHARGE CURRENT 0.2A/DIV t: 100ns/DIV 1s/DIV
FIGURE 13. SWITCHING WAVEFORMS AT CONSTANT CHARGE CURRENT MODE
FIGURE 14. SWITCHING WAVEFORMS AT TRICKLE CHARGE MODE
1
0.96 EFFICIENCY (%) VCSON = 12.6V 3 CELLS VCSON = 16.8V 4 CELLS VCSON = 8.4V 2 CELLS
0.92
0.88 0.84
0.8
0.76
0
0.5
1
1.5
2
2.5
3
3.5
4
CHARGE CURRENT (A)
FIGURE 15. EFFICIENCY vs CHARGE CURRENT
Functional Pin Descriptions
BOOT
Connect BOOT to a 0.1F ceramic capacitor to the PHASE pin and connect to the cathode of the bootstrap Schottky diode.
BGATE
BGATE power source select output. This pin drives an external P-channel MOSFET used to switch the battery as the system power source. When the voltage at the CSON pin is higher than the AC adapter output voltage at DCIN, BGATE is driven to low and selects the battery as the power source.
UGATE
UGATE is the high side MOSFET gate drive output.
SGATE
SGATE is the AC adapter power source select output. The SGATE pin drives an external P-MOSFET used to switch to AC adapter as the system power source.
LGATE
LGATE is the low side MOSFET gate drive output; swing between PGND and VDDP.
8
ISL6253
PHASE
The Phase connection pin connects to the high side MOSFET source, output inductor, and low side MOSFET drain.
PGND
PGND is the power ground. Connect PGND to the source of the low side MOSFET for the low side MOSFET gate driver.
VDD
VDD is an internal LDO output to supply the IC analog circuit. Connect a 1F ceramic capacitor to ground.
CSOP/CSON
CSOP/CSON are the battery charging current sensing positive/negative inputs. The differential voltage across CSOP and CSON is used to sense the battery charging current, and is compared with the charging current limit threshold to regulate the charging current. The CSON pin is also used as the battery feedback voltage to perform voltage regulation.
VDDP
VDDP is the supply voltage for the MOSFET gate driver. Connect a 4.7 resistor to VDD and a 1F ceramic capacitor to power ground.
ICOMP
ICOMP is a current loop error amplifier output. Connect a ceramic capacitor to ground.
CSIP/CSIN
CSIP/CSIN are the AC adapter current sensing positive/ negative inputs. The differential voltage across CSIP and CSIN is used to sense the AC adapter current, and is compared with the AC adapter current limit to regulate the AC adapter current.
VCOMP
VCOMP is a voltage loop amplifier output. Connect a ceramic capacitor in series with a resistor to ground.
GND
GND is an analog ground.
CELLS
This pin is used to select the battery voltage. CELLS = VDD for a 4S battery, CELLS = GND for a 3S battery pack, and CELLS = Float for a 2S battery pack.
DCIN
The DCIN pin is the input of the internal 5V LDO. Connect it to the AC adapter output. Connect DCIN to a 0.1F ceramic capacitor.
VADJ
VADJ adjusts battery regulation voltage. VADJ = VREF for 4.2V +5%/cell; VADJ = Floating for 4.2V/cell; VADJ = GND for 4.2V -5%/cell. Connect to a resistor divider from VREF to program the desired battery cell voltage between 4.2V -5% and 4.2V +5%.
ACSET
ACSET is an AC adapter detection input. Connect a resistor divider to an AC adapter.
ACPRN
ACPRN is an AC adapter present open drain output. ACPRN is active low when ACSET is higher than 1.26V; and active high when ACSET is lower than 1.26V.
CHLIM
CHLIM is the battery charge current limit set pin. CHLIM = VREF for 100mV, CHLIM = Floating for 65mV; CHLIM = GND for 30mV. Connect 3.3V for 127mV. Connect a resistor divider to program the charge current limit threshold between 30mV and 127mV.
DCSET
DCSET is a lower voltage adapter detection input (like aircraft power 15V). This allows power to the system, but power is not used to charge the battery.
ACLIM
ACLIM is the adapter current limit set pin. ACLIM = VREF for 103mV, ACLIM = Floating for 78mV, and ACLIM = GND for 53mV. Connect a resistor divider from VREF to program the adapter current limit threshold between 53mV and 103mV.
DCPRN
DCPRN is a DC adapter present open drain output. DCPRN is active low when DCSET is higher than 1.26V; and active high when DCSET is lower than 1.26V.
VREF
VREF is a reference output pin. Do not connect a decoupling capacitor.
EN
EN is the Charge Enable input. Connecting EN to high enables the charge control function, connecting EN to low disables charging functions.
ICM
ICM is the adapter current output. The output of this pin produces a voltage proportional to the adapter current.
9
ISL6253
DCIN
SGATE
CSIP
CSIN
DCSET
DCPRN
CA1 ICM
ACSET + ACPRN 1.26V gm3 ACLIM ADAPTER CURRENT LIMIT SET + MIN. CURRENT BUFFER ICOMP 2.1V + gm1 VCOMP 0.25V VOLTAGE VADJ SELECTOR MIN VOLTAGE BUFFER + CA2 PWM + BIAS Bias REGULATOR Regulator
3.1V/CELL UV VDD VCA2 Charge Current Set SET CHARGE CURRENT VREF Reference REFERENCE + CELLS
-
gm2 CA2 + CSOP CSON
GND
CHLIM
FIGURE 16. BLOCK DIAGRAM
10
-DCIN + CSON VDDP EN
1.26V
+ VDDP + BGATE VDD BOOT UGATE PHASE LGATE PGND + + +
ISL6253
INPUT: 7V TO 25V C9 0.1F CSON DCIN R9 10.2K 1% C12 1F VCC DIGITAL INPUT D/A OUTPUT OUTPUT R13: 100 A/D INPUT 5A INPUT C13 CURRENT LIMIT 0.1F 0.1 HOST C7 6.8nF ICM ACLIM VREF ICOMP VCOMP R6 10K C6 10nF VADJ DCSET DCSET SCL SDL TEMP BATCSON CSON 4 CELLS CELLS CELLS GND GND VDD C11 22F BATTERY PACK PGND PGND R5 100K C10 1F ACPRN CHLIM EN R7 4.7 4.7 VDD ACSET VDDP CSIN CSIN R3: 18 VDDP BOOT BOOT D2 UGATE UGATE PHASE PHASE LGATE LGATE Q2 D1 OPTIONAL C5 0.1F Q1 C1:10F C2 10F SGATE CSIP CSIP C3 0.1F R2 20m SYSTEM LOAD
Q3
R8 130K 1%
D3
ISL6253 ISL6253
L 15H
CSOP CSOP C4 1F R4 2.2
R1 25m 25m BAT+
AVDD/VREF
SCL SDL A/D INPUT GND
R10, R11, R12 10K FLOATING 4.2V/CELL
FIGURE 17. TYPICAL APPLICATION CIRCUIT 1
11
ISL6253
AC ADAPTER Q5 R13 100K 1% R14 10.5K 1% R8 130K 1% R9 10.2K 1% C8: 1F R5, R14 100K R7 4.7 VDD C9 0.1F CSON DCIN ACSET CSIP CSIP DCSET ISL6253 ISL6253 VDDP CSIN CSIN VDD BGATE BGATE VDDP ACPRN DCPRN CHLIM EN R13: 100 A/D INPUT C12 0.1F 5A INPUT CURRENT LIMIT C7 6.8nF R10,R11 R12:10k AVDD/VREF R6 10k SCL SDL A/D INPUT GND C6 10nF ICOMP VCOMP ICM ACLIM VREF BOOT BOOT D2 UGATE PHASE LGATE PGND CSOP C4 1F CSON CELLS GND VADJ FLOAT 4.2V/CELL SCL SDL TEMP BAT3 CELLS C11 22F R4 2.2 C5 0.1F Q2 D1 Optional L 15H Q1 C1:10F Q4 C3 0.1F R2 20m Q3
SGATE SGATE
SYSTEM LOAD C2 10F
C10: 1F
R3: 18
VCC DIGITAL INPUT DIGITAL INPUT D/A OUTPUT OUTPUT
HOST
R1 25m BAT+
BATTERY PACK
FIGURE 18. ISL6253 CONTROLLED TYPICAL APPLICATION 2
12
ISL6253 Theory of Operation
Introduction
The ISL6253 includes all of the functions necessary to charge 2 to 4 cell Li-Ion and Li-polymer batteries. A high efficiency synchronous buck converter is used to control the charging voltage and charging current up to 10 amps. The ISL6253 has input current limiting and analog inputs for setting the charge current and charge voltage; CHLIM inputs are used to control charge current and VADJ inputs are used to control charge voltage. The ISL6253 safely conditions over-discharged battery cells with a percentage of full charge current until the battery voltage exceeds 3.1V x number of series connected cells. When the battery voltage exceeds 3.1V x number of series connected cells, the ISL6253 charges the battery with constant charge current, set by CHLIM input, until the battery voltage rises to a programmed charge voltage set by VADJ input; then the charger begins to operate at constant voltage charge mode. The charger drives an adapter isolation p-channel MOSFET to efficiently switch in the adapter supply. ISL6253 is a complete power source selection controller for single battery systems and also aircraft power applications. ISL6253 drives a battery selector p-channel MOSFET to efficiently select between a single battery and the adapter. It controls the battery discharging MOSFET and switches to the battery when the AC adapter is removed, or, switches to the AC adapter when the AC adapter is inserted for a single battery system. The EN input allows shutdown of the charger from a micro-controller. The amount of adapter current is reported on the ICM output. Figure 16 shows the IC functional block diagram. The synchronous buck converter uses external N-channel MOSFETs to convert the input voltage to the required charging current and charging voltage. Figure 17 shows the ISL6253 typical application circuit 1 without power source selection function. The typical application circuit 2 shown in Figure 18 has automatic power source selection functionality and supports aircraft power applications. The voltage at CHLIM and the value of R1 sets the charging current. The DC-DC converter generates the control signals to drive two external N-channel MOSFETs to regulate the voltage and current set by the ACLIM, CHLIM, VADJ and CELLS inputs. The ISL6253 features a voltage regulation loop (VCOMP) and two current regulation loops (ICOMP). The VCOMP voltage regulation loop monitors CSON to ensure that its voltage never exceeds the voltage set by VADJ. The ICOMP current regulation loops regulate the battery charging current delivered to the battery to ensure that it never exceeds the charging current limit set by CHLIM; and the ICOMP current regulation loops regulate the input current drawn from the AC adapter to ensure that it never exceeds the input current limit set by ACLIM, and to prevent a system crash and AC adapter overload.
PWM Control
The ISL6253 employs a fixed frequency PWM current mode control architecture with a feed forward function. The feedforward function maintains a constant modulator gain of 11 to achieve fast line regulation as the buck input voltage changes. When the battery charge voltage approaches the input voltage, the DC-DC converter operates in dropout mode, where there is a timer to prevent the frequency from dropping into the audible frequency range. It can achieve a maximum duty cycle of up to 99.6%. An adaptive gate drive scheme is used to control the dead time between two switches. The dead time control circuit monitors the LGATE output and prevents the upper side MOSFET from turning on until LGATE is fully off, preventing cross-conduction and shoot-through. In order for the dead time circuit to work properly, there must be a low resistance, low inductance path from the LGATE driver to MOSFET gate, and from the source of MOSFET to PGND. The external Schottky diode is between the VDDP pin and BOOT pin to keep the bootstrap capacitor charged. The PWM controller is disabled when EN = GND, but the rest of the circuitry, including the AC or DC adapter detecting circuit and AC adapter current monitoring circuits, is still alive.
Setting the Battery Regulation Voltage
The ISL6253 uses a high-accuracy trimmed band-gap voltage reference to regulate the battery charging voltage. The VADJ input adjusts the charger output voltage, and the VADJ control voltage can vary from 0 to VREF (2.39V), providing a 10% adjustment range (from 4.2V -5% to 4.2V +5%) on CSON regulation voltage. An overall voltage accuracy of better than 0.5% is achieved. The per-cell battery termination voltage is a function of the battery chemistry. Consult the battery manufacturers to determine this voltage. Float VADJ to set the battery voltage VCSON = 4.2V x number of the cells, * Connect VADJ to VREF to set 4.41V x number of cells, * Connect VADJ to ground to set 3.99V x number of cells. Note that other battery charge voltages can be set by connecting a resistor divider from VREF to ground. The resistor divider should be sized to draw no more than 100A from VREF; or connect a low impedance voltage source like the D/A converter in the micro-controller. The programmed battery voltage per cell can be determined by the following equation:
V CELL = 0.175V VADJ + 3.99V (EQ. 1)
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ISL6253
Connect CELLS as shown in Table 1 to charge 2, 3, or 4 Li+ cells. When charging other cell chemistries, use CELLS to select an output voltage range for the charger. The internal error amplifier gm1 maintains voltage regulation. The voltage error amplifier is compensated at VCOMP. The component values shown in Figure 18 provide suitable performance for most applications. Individual compensation of the voltage regulation and current-regulation loops allows for optimal compensation.
TABLE 1. CELL NUMBER PROGRAMMING CELLS VCC GND Float CELL NUMBER 4 3 2
the input current by reducing the charging current, when the input current exceeds the input current-limit set point. System current normally fluctuates as portions of the system are powered up or down. Without input current regulation, the source must be able to supply the maximum system current and the maximum charger input current simultaneously. By using the input current limiter, the current capability of the AC adapter can be lowered, reducing system cost. The ISL6253 limits the battery charge current when the input current-limit threshold is exceeded, ensuring the battery charger does not load down the AC adapter voltage. An internal amplifier gm3 compares the voltage between CSIP and CSIN to the input current limit threshold voltage set by ACLIM. Connect ACLIM to REF, Float and GND for the fullscale input current limit threshold voltage of 103mV, 78mV, and 53mV, respectively, or use a resistor divider from VREF to ground to set the input current limit as the following equation:
1 0.05 I INPUT = ------ ---------------- V ACLIM + 0.053 R 2 VREF (EQ. 4)
Setting the Battery Charge Current Limit
The CHLIM input sets the maximum charging current. The current set by the current sense-resistor connects between CSOP and CSON. There are three default battery charge current-sense threshold voltages: 127mV for CHLIM = 3.3V, 100mV for CHLIM = VREF, 65mV for Float, and 30mV for ground. The full-scale differential voltage between CSOP and CSON is 100mV for CHLIM = VREF, so the maximum charging current is 4.0A for a 25m sensing resistor. Other battery charge current-sense threshold values can be set by connecting a resistor divider from VREF or VDD to ground, or by connecting a low impedance voltage source like a D/A converter in the microcontroller. The charge current limit threshold is given by:
1 0.07 I CHG = ------ ---------------- V CHLIM + 0.03 R 1 VREF (EQ. 2)
If the battery voltage is less than 3.0V/cell and the battery charging voltage is a percentage of the charging current in constant current charge mode, the trickle charge current limit threshold is given by:
1 I TR ,CHG = ------ ( 0.00157 x V CHLIM + 0.0037 R1 (EQ. 3)
When choosing the current sense resistor, note that the voltage drop across this resistor causes further power dissipation, reducing efficiency. The AC adapter current sense accuracy is very important. Use a 1% tolerance current-sense resistor. The highest accuracy of 3% is achieved with 103mV current-sense threshold voltage for ACLIM = VREF, but it has the highest power dissipation. For example, it has 400mW power dissipation for rated 4A AC adapter, and a 1W sensing resistor may have to be used. 4% and 6% accuracy can be achieved with 78mV and 53mV current-sense threshold voltage for ACLIM = Floating and ACLIM = GND, respectively. A low pass filter is recommended to eliminate the switching noise. Connect the resistor to the CSIN pin instead of the CSIP pin because the CSIN pin has lower bias current and less influence on the current-sense accuracy.
AC Adapter Detection
Connect the AC adapter voltage through a resistor divider to ACSET to detect when AC power is available, as shown in Figure 17. ACPRN is an open-drain output and is high impedance when ACSET is less than Vth,rise and active low impedance when ACSET is above Vth,fall . Vth,rise and Vth,fall are given by:
R8 V th, rise = ------ + 1 * V ACSET R9 R8 V th, fall = ------ + 1 * V ACSET - I hys R 8 R9 (EQ. 5)
When choosing the current sensing resistor, note that the voltage drop across the sensing resistor causes further power dissipation, reducing efficiency. However, adjusting CHLIM voltage to reduce the voltage across the current sense resistor R1 will degrade accuracy due to the smaller signal to the input of the current sense amplifier. There is a trade-off between accuracy and power dissipation. A low pass filter is recommended to eliminate switching noise. Connect the resistor to the CSOP pin instead of the CSON pin, as the CSOP pin has lower bias current and less influence on current-sense accuracy.
Setting the Input Current Limit
The total input current from an AC adapter, or other DC source, is a function of the system supply current and the battery-charging current. The input current regulator limits 14
Where Ihys is the ACSET input bias current hysteresis and VACSET = 1.235V (min), 1.26V (typ.) and 1.285V (max.). The hysteresis is Ihys R8, where Ihys = 2A (min.), 3.4A (typ.) and 4.8A (max.)
ISL6253
DC Adapter Detection
Connect the DC adapter voltage like aircraft power through a resistor divider to DCSET to detect when DC power is available, as shown in Figure 18. DCPRN is an open-drain output and is high impedance when DCSET is less than Vth,rise, and active low impedance when DCSET is above Vth,fall. Vth,rise and Vth,fall are given by:
R 13 V th, rise = --------- + 1 * V DCSET R 14 R 13 V th, fall = --------- + 1 * V DCSET - I hys R 13 R 14 (EQ. 6)
DCSET is tied to a resistor divider sensing the adapter voltage. When a user is plugged into the 15V airplane supply and their battery is lower than 15V, the MOSFET driven by BGATE (see Figure 18) is turned off and keeps the battery from supplying the system bus. The comparator looking at CSON and DCIN has 300mV of hysteresis to avoid chattering. For aircraft power applications the ISL6253 is only able to support 2S and 3S battery packs when disabling the charging function based on DCPRN and ACPRN signals. For 4S battery packs, DCSET = 0 and the DCPRN signal is not available to support aircraft power applications.
Short Circuit Protection and 0V Battery Charging
Since the battery charger will regulate the charge current to be trickle charge current, as long as the battery voltage is below 3.0V/cell, it automatically has short circuit protection and is able to provide the trickle charge current and "wakeup" an extremely discharged battery.
Where Ihys is the DCSET input bias current hysteresis and VACSET = 1.235V (min), 1.26V (typ.) and 1.285V (max.). The hysteresis is IhysR13, where Ihys = 2A (min.), 3.4A (typ.) and 4.8A (max.)
Current Measurement
Use ICM to monitor the input current being sensed across CSIP and CSIN. The output voltage range is 0 to 2.5V. The voltage of ICM is proportional to the voltage drop across CSIP and CSIN, and is given by the following equation:
ICM = 19.22 * I INPUT * R 2 (EQ. 7)
Over Temperature Protection
If the die temp exceeds 150C, it stops charging. Once the die temp drops below 130C, charging will start up again.
Application Information
The following battery charger design refers to the typical application circuit in Figure 17, where a typical battery configuration of 4S2P is used. This section describes how to select the external components including the inductor, input and output capacitors, switching MOSFETs, and current sensing resistors.
where IINPUT is the DC current drawn from the AC adapter. ICM has 5% accuracy. Connect a low pass filter to ICM to bypass the switching frequency noise.
LDO Regulator
VDD provides a 5.0V supply voltage from the internal LDO regulator from DCIN and can deliver up to 30mA of current. This 30mA current is only used to supply the analog and logic circuits for the IC and power the gate drivers. The MOSFET drivers are powered by VDDP, and VDDP connects to VDD through an external low pass filter. Bypass VDDP and VDD with a 1F capacitor.
Inductor Selection
The inductor selection has trade-offs between cost, size and efficiency. For example, the lower the inductance, the smaller the size, but ripple current is higher. This also results in higher ac losses in the magnetic core and the windings, which decrease the system efficiency. On the other hand, the higher inductance results in lower ripple current and smaller output filter capacitors, but it has higher DCR (dc resistance of the inductor) loss, and has slower transient response. So, the practical inductor design is based on the inductor ripple current being (15-20)% of the maximum operating dc current at maximum input voltage. The required inductance can be calculated from:
V BAT V IN ,MAX - V BAT L = -------------------------------------------- ---------------------------I L V IN ,MAX f s (EQ. 8)
Supply Isolation
If the voltage across the adapter sense resistor R2 is typically greater than 8.5mV, the p-channel MOSFET controlled by SGATE is turned on reducing the power dissipation. If the voltage across the adapter sense resistor R2 is less than 2mV, SGATE turns off the p-channel MOSFET isolating the adapter from the system bus.
Battery Power Source Selection and Aircraft Power Application
The battery voltage is monitored by CSON. If the battery voltage measured on CSON is less than the adapter voltage measured on DCIN, then the p-channel MOSFET controlled by BGATE turns off. If it is greater, then BGATE turns on the battery discharge p-channel MOSFET to minimize the power loss. In the meantime, it also disables charging function and turns off the AC adapter isolation p-channel MOSFET controlled by SGATE. If designing for airplane power, 15
where VIN,MAX, VBAT, and fs are the maximum input voltage, battery voltage and switching frequency, respectively. The inductor ripple current IL is found from:
I L = 30% I BAT ,MAX (EQ. 9)
where the maximum peak-to-peak ripple current is 30% of the maximum charge current used.
ISL6253
For VIN,MAX = 20V, VBAT = 16.8V, IBAT,MAX = 4A, and fs = 300kHz, the calculated inductance is 12.8H. Choosing the closest standard value gives L = 15H. Ferrite cores are often the best choice since they are optimized at 300kHz to 600kHz operation with low core loss. The core must be large enough not to saturate at the peak inductor current IPeak:
1 I Peak = I BAT ,MAX + -- I L 2 (EQ. 10)
Output Capacitor Selection
The output capacitor in parallel with the battery is used to absorb the high frequency switching ripple current and smooth the output voltage. The RMS value of the output ripple current Irms is given by:
V IN ,MAX I RMS = ----------------------- D ( 1 - D ) 12 L f s (EQ. 11)
charger application, the input voltage of the synchronous buck converter is equal to the AC adapter output voltage, which is relatively constant. The maximum efficiency is achieved by selecting a high side MOSFET that has the conduction losses equal to the switching losses. Ensure that the ISL6253 LGATE gate driver can supply sufficient gate current to prevent it from conduction, which is due to the injected current into the drain-to-source parasitic capacitor (Miller capacitor Cgd), and caused by the voltage rising rate at the phase node at the moment of the high-side MOSFET turning on; otherwise, cross-conduction problems may occur. Reasonably slowing the turn-on speed of the highside MOSFET, by connecting a resistor between the BOOT pin and gate drive supply source, and the high sink current capability of the low-side MOSFET gate driver, helps reduce the possibility of cross-conduction. For the high-side MOSFET, the worst-case conduction losses occur at the minimum input voltage:
V OUT 2 P Q1 ,Conduction = --------------- I BAT R DSON V IN (EQ. 13)
where the duty cycle D is the ratio of the output voltage (battery voltage) over the input voltage for continuous conduction mode, which is typical operation for a battery charger. During the battery charge period, the output voltage varies from its initial battery voltage to the rated battery voltage; therefore, the duty cycle change can be in the range of between 0.375 and 0.63 for the minimum battery voltage of 7.5V (2.5V/Cell) and the maximum battery voltage of 12.8V. The maximum RMS value of the output ripple current occurs at the duty cycle of 0.5 and is expressed as:
V IN ,MAX I RMS = ----------------------4 12 Lf s (EQ. 12)
The optimum efficiency occurs when the switching losses equal the conduction losses. However, it is difficult to calculate the switching losses in the high-side MOSFET since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include: the MOSFET internal gate resistance, gate charge, threshold voltage, stray inductance, and pull-up and pulldown resistance of the gate driver. The following switching loss calculation provides a rough estimate:
(EQ. 14) Q gd Q gd 1 1 -PQ1 ,Switching = -- V IN I LV f s ----------------------- + -- V IN I LP f s ---------------- + Q rr VIN f s I g ,source 2 I g , sin k 2
For VIN,MAX = 20V, L = 15H, and fs = 300kHz, the maximum RMS current is 0.32A. A typical 10F or 22F ceramic capacitor is a good choice to absorb this current, and also has very small size. The tantalum capacitor has a known failure mechanism when subjected to high surge current. EMI considerations usually make it desirable to minimize ripple current in the battery leads. Beads may be added in series with the battery pack to increase the battery impedance at 300kHz switching frequency. Switching ripple current splits itself between the battery and the output capacitor, depending on the ESR of the output capacitor and the battery impedance. If the ESR of the output capacitor is 20m and the battery impedance is raised to 2 with a bead, then only 1% of the ripple current will flow in the battery.
where Qgd is drain-to-gate charge; Qrr is total reverse recovery charge of the body-diode in low side MOSFET; ILV is inductor valley current; ILP is Inductor peak current; and Ig,sink and Ig,source are the peak gate-drive source/sink current of Q1, respectively. Achievement of low switching losses requires low drain-togate charge, Qgd. Generally, the lower the drain-to-gate charge, the higher the on-resistance; therefore, there is a trade-off between the on-resistance and drain-to-gate charge. Good MOSFET selection is based on the Figure of Merit (FOM), which is the product of the total gate charge and on-resistance. Usually, the smaller the value of FOM, the higher the efficiency for the same application. For the low-side MOSFET, the worst-case power dissipation occurs at minimum battery voltage and maximum input voltage:
V OUT 2 P Q2 = 1 - --------------- I BAT R DSON V IN (EQ. 15)
MOSFET Selection
The notebook battery charger synchronous buck converter has input voltage from the AC adapter output. The maximum AC adapter output voltage does not exceed 25V; therefore, a 30V logic MOSFET should be used. The high side MOSFET must be able to dissipate the conduction losses plus the switching losses. For the battery 16
ISL6253
Choose a low-side MOSFET that has the lowest possible on-resistance, has a moderate-sized package like SO-8 and is reasonably priced. The switching losses are not an issue for the low side MOSFET because it operates at zerovoltage-switching. Choose a Schottky diode in parallel with low-side MOSFET Q2 with a forward voltage drop low enough to prevent the low-side MOSFET Q2 body-diode from turning on during the dead time. This also reduces the power loss in the high-side MOSFET associated with the reverse recovery of the lowside MOSFET Q2 body diode. As a general rule, select a diode with a DC current rating equal to one-third of the load current. One option is to choose a combined MOSFET and Schottky diode in a single package. The integrated packages may work better in practice because there is less stray inductance due to a short connection. This Schottky diode is optional and may be removed if efficiency loss can be tolerated. In addition, ensure that the required total gate drive current for the selected MOSFETs is less than 26mA. The total gate charge for the high-side and low-side MOSFETs is limited by the following equation:
I GATE Q GATE ---------------fs (EQ. 16) TABLE 2. COMPONENT LIST PARTS C1, C2 PART NUMBERS AND MANUFACTURER 10F/25V ceramic capacitor, TDK, C4532X7R1E106M
C3, C5, C9, C12 0.1F/50V ceramic capacitor C4, C8, C10 C6 C7 C11 D1 D2, D3 L Q1 Q2 Q3 R1 R2 R3 1F/10V ceramic capacitor, Taiyo Yuden LMK212BJ105MG 10nF ceramic capacitor 6.8nF ceramic capacitor 10F or 22F/25V/10m ceramic capacitor TDK, C5750X7R1E226M 30V/3A Schottky Diode, EC31QS03L, Nihon (optional) 100mA/30V Schottky Diode, Central Semiconductor 15H/4.5A/20m, Sumida, CDRH127-150 30V/14m, IRF7811AV, International Rectifier 30V/30m, FDS6612A, Fairchild -30V/9.5m, Si4413DY, Siliconix 25m, 1%, LRC-LR2010-01-R025-F, IRC 20m, 1%, LRC-LR2010-01-R020-F, IRC 18, 5%, (0805) 2.2, 5%, (0805) 100k, 5%, (0805) 10k, 5%, (0805) 4.7, 5%, (0805) 130k, 1%, (0805) 10.2k, 1%, (0805) 10k, 5%, (0805) 100, 5%, (0805) 100k, 5%, (0805)
where IGATE is the total gate drive current and should be less than 26mA. Substituting IGATE = 26mA and fs = 300kHz into the above equation yields a total gate charge which should be less than 86nC; therefore, the ISL6253 easily drives the battery charge current up to 10A.
R4 R5 R6 R7 R8 R9 R10, R11, R12
Input Capacitor Selection
The input capacitor absorbs the ripple current from the synchronous buck converter, which is given by:
V OUT ( V IN - V OUT ) I rms = I BAT ---------------------------------------------------V IN (EQ. 17)
R13 R14
This RMS ripple current must be smaller than the rated RMS current in the capacitor data sheet. Non-tantalum chemistries (ceramic, aluminum, or OSCON) are preferred due to their resistance to power-up surge currents when the AC adapter is plugged into the battery charger. For Notebook battery charger applications, a ceramic capacitor or a polymer capacitor from Sanyo is recommended due to its small size and reasonable cost. Table 2 shows the component lists for the typical application circuit in Figure 18.
Loop Compensation Design
ISL6253 uses constant frequency current mode control architecture to achieve fast loop transient response. Accurate current sensing resistors in series with the output inductor is used to regulate the charge current, and the sensed current signal is injected into the voltage loop to achieve current mode control to simplify the loop compensation design. The inductor is not considered as a state variable for current mode control, and the system becomes a single order system. It is much easier to design a type II compensator to stabilize the voltage loop than voltage mode control. Figure 19 shows the small signal model of the synchronous buck regulator.
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ISL6253
PWM Comparator Gain Fm
The PWM comparator gain Fm for peak current mode control is given by:
1 d F m = ---------------- = ---------------- V PWM v comp (EQ. 18)
If Ti(S)>>1, then the above equation can be simplified as follows:
S 1 + ----------V FB R o + R L esr A v ( S ) 1---------- -------------------- --------------------- ----------------, p -------------Lv ( S ) = S He ( S ) V o R TV Ro Co 1 + -----p (EQ. 25)
where VPWM is the peak-peak voltage of the PWM ramp signal.
Current Sampling Transfer Function He(S)
In current loop, the current signal is sampled every switching cycle. It has the following transfer function:
S S H e ( S ) = ------ + -------------- + 1 2 Q nn n 2 where Qn and n are given by Q n = - -- , n = f s , respectively.
2
Where RTV is the trans-resistance due to the current information fed into the voltage loop. From the above equation, it is shown that the system is a single order system, which has a single pole located at p before the half switching frequency. Therefore, a simple type II compensator can be easily used to stabilize the system. Figure 20 shows the type II compensator, and its transfer function is expressed as follows:
^ iin
+
(EQ. 19)
^ iL
L
^ Vo
Power Stage Transfer Functions
Transfer function F1(S) from control to output voltage is:
S 1 + ---------- esr vo F 1 ( S ) = ----- = V in ------------------------------------- 2 d S S ------ + -------------- + 1 2 Q op o Co 1 1 Where esr = -------------- , Q p R o ------ , o = -------------L Rc Co LC o (EQ. 20)
+
^ vin
^ ILd 1:D
^ Vind Rc RT Ro Co
^ d Fm
Ti(S) K
Transfer function F2(S) from control to inductor current is,
S 1 + -----(EQ. 21) z V in io 1 F 2 ( S ) = --- = -------------------- -------------------------------------- where z ------------- Ro Co d Ro + RL S2 S ------ + -------------- + 1 2 Q op o
+
He(S) V^ comp
Tv(S) -Av(S)
FIGURE 19. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK REGULATOR
Current loop gain Ti(S) is expressed as the following equation:
T i ( S ) = R T F m F 2 ( S )H e ( S ) (EQ. 22)
Vo
VFB
where RT is the trans-resistance in current loop. RT is usually equal to the product of the current sensing resistance of the current amplifier. For ISL6253, RT = 24R1. The voltage gain with open current loop is:
T v ( S ) = KF m F 1 ( S )A v ( S ) V Vo (EQ. 23)
+ gm
VREF
VCOMP
R1 C1
C2
FB where K = ---------- , VFB is the feedback voltage of the voltage
error amplifier.
FIGURE 20. TYPE II COMPENSATOR
The Voltage loop gain with current loop closed is given by:
Tv ( S ) L v ( S ) = ----------------------1 + Ti ( S ) (EQ. 24)
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ISL6253
Figure 20 shows the type II compensator and its transfer function is expressed as follows:
S 1 + -------- cz gm v comp -------------------- ----------------------------A v ( S ) = ---------------- = C1 + C2 S v FB S 1 + ---------
cp
PCB Layout Considerations
Power and Signal Layer Placement on the PCB
As a general rule, power layers should be close together, either on the top or bottom of the board, with signal layers on the opposite side of the board. For example, layer arrangement on a 4 layer board is shown below: Layer 1: Small signal external components Layer 2: Signal Ground Layer 3: Power Ground Layer 4: Bottom Layer: Power MOSFET, Inductors and other Power traces Separate the power voltage and current flowing path from the control and logic level signal path. The controller IC will stay on the signal layer, which is isolated by the signal ground to the power signal traces.
(EQ. 26)
1 1 2 where cz = -------------- , cp = ---------------------R1 C1
C +C
R1 C1 C2
Compensator design goal: * High DC gain
11 * Loop bandwidth fc: -- - ------ f s 5 30
* Gain margin: >10dB * Phase margin: 40 The compensator design procedure is as follows:
1 1. Put compensator zero at cz = ( 1 - 3 ) -------------RC
oo
Component Placement
The power MOSFET should be close to the IC so that the gate drive signal, the LGATE, UGATE, PHASE, and BOOT traces can be short. Place the components in such a way that the area under the IC has fewer noise traces with high dv/dt and di/dt, such as gate signals and phase node signals. SIGNAL GROUND AND POWER GROUND CONNECTION At minimum, a reasonably large area of copper, which will shield other noise couplings through the IC, should be used as signal ground beneath the IC. The best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each side, where there is little noise; a noisy trace beneath the IC is not recommended. GND AND VDD PIN At least one high quality ceramic decoupling cap should be used to cross the GND and VDD pins. The decoupling cap can be put close to the IC. LGATE PIN This is the gate drive signal for the bottom MOSFET of the buck converter. The signal going through this trace has both high dv/dt and high di/dt, and the peak charging and discharging current is very high. These two traces should be short, wide, and away from other traces. There should be no other traces in parallel with these traces on any layer. PGND PIN The PGND pin should be laid out to the negative side of the relevant output cap with separate traces. The negative side of the output capacitor must be close to the source node of the bottom MOSFET.
2. Put one compensator pole at zero frequency to achieve high DC gain, and put another compensator pole at either esr zero frequency or half switching frequency, whichever is lower. The loop gain Tv(S) at cross over frequency of fc has unity gain. Therefore, the compensator resistance R1 is determined by:
2f c V o C o R T R 1 = ----------------------------------g m V FB (EQ. 27)
where gm is the trans-conductance of the voltage error amplifier. Compensator capacitor C1 is then given by:
C1 1 C 1 = -----------------, C 2 = ----------------------------------------2R 1 C 1 f esr - 1 R 1 cz (EQ. 28)
Example: Vin = 20V, Vo = 16.8V, Io = 4A, fs = 300kHz, Co = 22F/10m, L = 15H, gm = 250s, RT = 0.15 (Rcs = 25m, Ac = 6), VFB = 2.1V, VPWM = VIN/11, fc = 15kHz, then compensator resistance R1 = 10k. Put the compensator zero at 1.7kHz, and put the compensator pole at esr zero which is 725kHz. The compensator capacitors are: C1 = 10nF, C2 = 22pF Such small C2 may not be necessary since it does not affect the phase and gain at such high frequency.
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ISL6253
PHASE PIN This trace should be short, and positioned away from other weak signal traces. This node has a very high dv/dt with a voltage swing from the input voltage to ground. No trace should be in parallel with it. This trace is also the return path for UGATE. Connect this pin to the high-side MOSFET source. UGATE PIN This pin has a square shape waveform with high dv/dt. It provides the gate drive current to charge and discharges the top MOSFET with high di/dt. This trace should be wide, short, and away from other traces similar to the LGATE. BOOT PIN The BOOT pins di/dt is as high as the UGATE; therefore, this trace should be as short as possible. CSOP, CSON PINS The current sense resistor connects to the CSON and the CSOP pins through a low pass filter. The CSON pin is also used as the battery voltage feedback. The traces should be away from the high dv/dt and di/di pins like the PHASE and BOOT pins. In general, the current sense resistor should be close to the IC. Other layout arrangements should be adjusted accordingly. EN PIN This pin stays high at enable mode and low at idle mode, and is relatively robust. Enable signals should refer to the signal ground. DCIN PIN This pin connects to AC adapter output voltage, and should be less noise sensitive.
Copper Size for the Phase Node
The capacitance of PHASE should be kept very low to minimize ringing. It would be best to limit the size of the PHASE node copper in strict accordance with the current and thermal management of the application.
Identify the Power and Signal Ground
The input and output capacitors of the converters, and the source terminal of the bottom switching MOSFET PGND should connect to the power ground. The other components should connect to signal ground. Signal and power ground are tied together at one point.
Clamping Capacitor for Switching MOSFET
It is recommended that ceramic caps be used closely connected to the drain of the high-side MOSFET and the source of the low-side MOSFET. This capacitor reduces the noise and the power loss of the MOSFET.
20
ISL6253 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
2X 0.15 C A A 9 D1 D1/2 6 INDEX AREA N 1 2 3 E1/2 E1 9 2X 0.15 C B 2X 0.15 C A 4X C 0.08 C SEATING PLANE SIDE VIEW NX b 4X P D2 (DATUM B) 4X P 1 (DATUM A) 6 INDEX AREA NX L Ne 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 2 3 E2 7 E2/2 8 (Ne-1)Xe REF. D2 2N 5 0.10 M C A B 7 8 NX k A3 A1 0 TOP VIEW A2 A / / 0.10 C B E/2 E 2X 0.15 C B D D/2
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L 0.25 0.50 2.95 2.95 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.23 5.00 BSC 4.75 BSC 3.10 5.00 BSC 4.75 BSC 3.10 0.50 BSC 0.60 28 7 8 7 0.60 12 0.75 0.15 3.25 3.25 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5,8 9 7,8 9 7,8 8 10 2 3 3 9 9 Rev. 0 02/03 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.
9
L1 N Nd Ne P
9 CORNER OPTION 4X
C L
SECTION "C-C" C L
8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
L1 e CC
10
L L1 e
10
L
TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE
21
ISL6253 Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA 0.25 0.010 h x 45 L GAUGE PLANE 0.25(0.010) M BM
M28.15
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150" WIDE BODY) INCHES SYMBOL A A1 A2 B C D
A2 C 0.10(0.004) C AM BS
MILLIMETERS MIN 1.35 0.10 0.20 0.18 9.81 3.81 5.80 0.26 0.41 28 0 MAX 1.75 0.25 1.54 0.30 0.25 10.00 3.98 6.19 0.49 1.27 8 NOTES 9 3 4 5 6 7 Rev. 1 6/04
MIN 0.053 0.004 0.008 0.007 0.386 0.150 0.228 0.0099 0.016 28 0
MAX 0.069 0.010 0.061 0.012 0.010 0.394 0.157 0.244 0.0196 0.050 8
A1
e
B 0.17(0.007) M
E e H h L N
0.025 BSC
0.635 BSC
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 22

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